The present invention relates to an image display apparatus, and more particularly to a control circuit for an image memory which stores image information of a bit map type display.
In a prior art image display apparatus, a data in an image memory is partially modified in the following manner. When a character pattern is transferred from a character generator to the image memory, a microcomputer (MPU):
(1) temporarily fetches data stored at a corresponding address of the image memory, PA0 (2) shifts a pattern to be added, to a display bit position, PA0 (3) masks the data read from the image memory to extract a portion not to be modified, and masks the shifted character pattern to extract only the bits to be written, and logically ORes them, and PA0 (4) writes the logically ORed data into the same address of the image memory.
In the MPU, the bit processing speed is slow and a command to shift a plurality of bits is executed by repetitively executing a command of one-bit shift.
In Japanese Unexamined Patent Publication No. 59-90156, it has been proposed to modify the data bit by bit by an external circuit comprising a shift register and a counter rather than by the MPU. However, even in this system, there is a delay time between the end of the write operation by the MPU and the end of the operation of the shift register and the writing of the data into the image memory. Accordingly, the MPU cannot instruct continuous writing into the image memory. Therefore, it is suitable for writing one bit but is not appropriate for writing a large amount of data.